The present disclosure relates to a laminated wiring board suitable for mounting of a semiconductor integrated circuit such as a double data rate (DDR)-synchronous DRAM (SDRAM).
A laminated wiring board is known in which at least one semiconductor device (integrated circuit (IC)) that operates by a high-speed clock signal is mounted together with other electronic parts such as a controller IC that controls the semiconductor device.
In particular, small size and high-density mounting are required for a (printed) wiring board mounted in portable electronic apparatus, and increase in the number of stacked layers is promoted in response to this request.
For example, in a multilayer motherboard mounted in small portable apparatus or a package board mounted on a motherboard as one kind of electronic parts, one laminated wiring board is realized by stacking wiring boards of four, six, eight, or more layers. Each wiring board is obtained by forming an electrically-conductive layer such as a copper foil on a substrate or a tape (insulating layer) of e.g. a resin. Wiring is formed by patterning the electrically-conductive layer. Conduction between the wiring layers is realized by a through-via or another technique. There are a technique in which through-vias are mechanically formed and conduction between wiring layers is established by e.g. copper plating, and a technique in which conductive measures are provided in each layer and conduction between wiring layers is established when the layers are built up.
Such a laminated wiring board has a multilayer structure obtained by stacking plural wiring layers with the intermediary of an electrically-conductive layer between the layers.
In the laminated wiring board, layers are provided such as a power supply layer in which a power supply pattern as a pattern connected to a power supply is provided and a ground layer in which a ground pattern as a pattern connected to the ground is provided. Furthermore, for example, in a laminated wiring board composed of six layers, one power supply layer and one or two ground layers are provided as inner layers, i.e. layers existing inside the laminated wiring board, in many cases. Normally a signal wiring layer in which a pattern of a signal line is provided is so disposed as to be stacked adjacent to the ground layer with the intermediary of an insulating layer.
For size reduction (reduction in the occupation area and the thickness), these wiring layers are mounted at high density to form the laminated wiring board.
Therefore, in the laminated wiring board for mounting a high-speed operation IC, there is a problem that the distance of the signal wiring layer from the power supply layer is long particularly. For example, in the case of the DDR-SDRAM, it is difficult to dispose the signal wiring layer in which a pattern of signal wiring driven at the DDR (double data rate) is provided as an inner layer across a sufficiently-short distance from the power supply layer or an outer layer closer to the outside, because of high-density mounting. Furthermore, due to increase in the distance between the power supply layer and the ground layer, the capacitive coupling and inductive coupling of the power supply section become small. Therefore, the impedance of the path to supply the power supply voltage and the ground potential to the circuit that treats a high-speed signal becomes high.
Due to this impedance increase, in a laminated wiring board such as a DDR memory interface board, simultaneous switching noise (SSO) and so forth of a high-speed operation LSI is readily superimposed on the power supply and the ground. As a result, temporal variation (jitter) or inter-signal interference (crosstalk) of signal potential transition becomes larger and the lowering of the characteristics of the LSI occurs.
To suppress the impedance increase of the power supply wiring and the ground wiring, several laminated wiring board structures have been proposed regarding the arrangement of wiring layers (refer to the following Patent Documents 1 to 3).
In Patent Document 1 (Japanese Patent Laid-open No. 2002-299840), a laminated wiring board in which seven layers that are composed of wiring layers and insulating layers and are represented by symbols L1 to L7 are provided is disclosed (see FIG. 1 and so forth of cited document 1). For example, in FIG. 1 of cited document 1, the lowermost layer is L7. As the reference number of the symbol “L” becomes larger, a larger number of layers are stacked on the upper side of this layer. The uppermost layer is L1. A wiring layer is formed also on the back surface of the lowermost layer L7.
In the wiring layer arrangement of Patent Document 1, a power supply layer to which a power supply voltage is supplied is employed as the fifth layer L5, and a ground layer is provided as the fourth layer L4, which is the upper adjacent layer. The second layer L2 and the seventh layer L7 are also ground layers. Signal line wiring layers are provided as the first layer L1, the third layer L3, and the sixth layer L6, which are adjacent to the ground layers.
According to such stacking arrangement of wiring layers, the ground layer is disposed as the fourth layer L4 adjacent to (on the upper side of) the fifth layer L5, which is the power supply layer, and thereby the capacitive coupling and the inductive coupling between both wiring layers are made large. Thus, the impedance of each wiring layer becomes low and potential variation due to noise and so forth occurs less readily in both wiring layers.
In Patent Document 2 (Japanese Patent Laid-open No. 2003-218541), a structure in which a power supply layer 14 is sandwiched by ground layers 13a and 13b from both sides is disclosed (refer to FIG. 1 of cited document 2). Thus, in the power supply layer and the ground layer, the resistance against noise due to reduction in the impedance is higher compared with that in the above-described cited document 1.
In Patent Document 3 (Japanese Patent Laid-open No. 2008-235364), the assignee of the present application has already proposed a laminated wiring board structure in which two power supply layers L3 and L4 are disposed with the intermediary of an insulating layer (see FIG. 2 of cited document 3). Two ground layers L2 and L5 are provided on both sides of the two power supply layers L3 and L4 with the intermediary of each insulating layer. Signal wiring layers are provided as the uppermost layer L1and the lowermost layer L6.